The present invention generally relates to memory devices and fabrication thereof, and more particularly, to floating gate nonvolatile memory cells and fabrication thereof.
Semiconductor memory devices may be classified into volatile memory devices and non-volatile memory devices. Generally, a volatile memory device loses data stored therein when a power supply to the cell is removed. In contrast, a non-volatile memory device typically does not lose data (or loses data at a relatively slow rate) when power is removed. DRAM and SRAM devices are generally classified as volatile memory devices and flash memory devices are classified as nonvolatile memory devices.
FIG. 1 is a cross-sectional view of a unit cell of a conventional flash memory device. FIG. 2 is an energy band diagram for a program operation of the flash memory cell, taken along a line I–I′ of FIG. 1.
Referring to FIGS. 1 and 2, a gate pattern 6 comprises a tunnel oxide layer 2, a floating gate 3, a control gate insulation layer 4, and a control gate electrode 5 that are stacked on a substrate 1. Respective impurity diffusion layers 7 are formed in active regions at respective sides of the gate pattern 6. The impurity diffusion layers 7 correspond to source/drain regions, and a portion of the substrate 1 under the gate pattern 6 corresponds to a channel region 8. The floating gate 3 (where electrons are stored) is electrically isolated from the channel region.
The control gate electrode 5 plays a role in programming or erasing. In a program operation, a program voltage is applied to the control gate electrode 5 and a reference voltage is applied to the substrate 1 to cause electrons in the substrate 1 to tunnel through the tunnel oxide layer 2 and flow into the floating gate 3. In an erase operation, an erase voltage is applied to the control gate electrode 5 and a reference voltage is applied to the substrate 1 to cause electrons stored in the floating gate 3 to be released to the substrate 1. Typically, the program and erase voltages are higher than a power supply voltage applied to the device.
In the flash memory cell described above, electrons tunnel through the tunnel oxide layer 2 according to a Fowler-Nordheim tunneling mechanism (FN tunneling). Electrons typically tunnel through the tunnel oxide layer 2 across throughout the channel region 8. The manner in which electrons (or electrons and holes) tunnel through the tunnel oxide layer 2 will now be explained with reference to the energy band diagram of FIG. 2.
When data is written in the flash memory cell (i.e., during a program operation), a program voltage is applied to the control gate electrode 5, a reference voltage is applied to the substrate 1 and the source/drain regions 7 float. The program voltage is higher than the reference voltage. Therefore, the energy band of the tunnel oxide layer 2 inclines to thin widths of the upper and lower energy band. Thus, the electrons of a conduction band Ec of the channel region 8 tunnel through the thinned upper energy band by FN tunnel to the floating gate 3 (step A). The electrons that FN tunnel may increase as the width 10 of the upper energy band becomes thinner. In this case, holes in a valance band Ev of the floating gate 3 tunnel the thinned lower energy band of the tunnel oxide layer 2 to transfer to the channel region 8 (step B). The holes that tunnel also increase as the width 11 of the lower energy band decreases. The number of holes that tunnel generally is less than the number of electrons that tunnel due to the effective mass of the individual holes, which is greater than that of the individual electrons.
As flash memory devices become more highly integrated and low power consumption becomes increasingly desirable, it may be desirable to reduce program and erase voltages. In addition, improved endurance of flash memory devices is also desirable.
Endurance of a flash memory cell is generally reduced by repetition of program and erase operations. In particular, interface traps may be formed at the interface of the tunnel oxide layer 2 by the electrons that tunnel therethrough. The electrons may be caught in the interface traps when tunneling, such that the endurance of the flash memory device may be degraded. Holes, having an effective mass larger than electrons, can seriously affect the generation of the interface trap.